1. Field of the Invention
The present invention relates to a solar cell, and more particularly, to a method of manufacturing a solar cell that improves electro-optical properties and maximizes efficiency of the solar cell.
2. Discussion of the Related Art
A solar cell is a semiconductor device that converts solar energy into electric energy. The solar cell includes a junction formed by joining a p-type semiconductor and an n-type semiconductor together in contact and has a basic structure of a diode.
In general, a solar cell includes a structure of a p-n junction semiconductor layer, in which a p-type semiconductor layer and an n-type semiconductor layer are disposed between opposite electrodes.
For photovoltaic energy conversion of a solar cell, electrons exist asymmetrically in the structure of the p-n junction semiconductor layer. Namely, in the structure of the p-n junction semiconductor layer, the n-type semiconductor layer has high electron density and low hole density, and the p-type semiconductor layer has low electron density and high hole density. Therefore, in a thermal equilibrium state, imbalance of electric charges is caused by diffusion due to different densities of carriers in the p-n junction semiconductor layer. According to this, an electric field is induced, and there is no more diffusion of the carries. At this time, when light having a larger energy than a band gap energy, which is an energy difference between a conduction band and a valence band, is irradiated to the p-n junction semiconductor layer, electrons receiving the energy are excited from the valence band to the conduction band, and holes are generated in the valence band. The electrons excited to the conduction band freely move. The free electrons and the holes generated as mentioned above may be referred to as excess carriers, and the excess carriers are diffused by the difference of the density in the valence band or the conduction band. Here, the excess carriers, that is, the excited electrodes in the p-type semiconductor layer and the holes generated in the n-type semiconductor layer, are defined as minority carriers, while the carriers in the p-type and n-type semiconductor layers before joining, that is, the holes in the p-type semiconductor layer and the electrons in the n-type semiconductor layer, are defined as majority carriers. Flow of the majority carriers is blocked by an energy barrier due to the electric field. However, the electrons, the minority carriers in the p-type semiconductor layer, can move to the n-type semiconductor layer. The diffusion of the minority carriers causes a potential drop in the p-n junction semiconductor layer. When the p-n junction semiconductor layer is connected to an outer circuit, this can be used as an electric cell due to an electromotive force generated at both ends of the p-n junction semiconductor layer.
Accordingly, a solar cell further includes a transparent electrode and a rear electrode at outer surfaces of the p-n junction semiconductor layer. The transparent electrode has an uneven surface so that light from an external light source is efficiently provided to the p-n junction semiconductor layer.
FIGS. 1A to 1F are views of illustrating a solar cell in steps of a method of manufacturing the same according to the related art.
In FIG. 1A, a transparent conductive layer 4 is formed on a substantially entire surface of a transparent insulating substrate 1 by depositing a transparent conductive oxide (TCO) using a sputtering apparatus (not shown) under temperature of 300 to 600 degrees of Celsius. The transparent conductive layer 4 has an even surface. At this time, the deposition of the transparent conducive oxide by a sputtering method under high temperature is accompanied with partial crystallization, and the transparent conductive layer 4 includes randomly micro-crystallized portions and amorphous portions between the crystallized portions.
In FIG. 1B, embossed and depressed patterns 6 are formed at the surface of the transparent conductive layer 4 by dipping the substrate 1 including the transparent conductive layer 4 into an etching bath (not shown) filled with etchant, which reacts with the transparent conductive oxide, or by spraying etchant onto the transparent conductive layer 4. Here, time for exposing the transparent conductive layer 4 to the etchant is properly controlled, and the transparent conductive layer 4 is not completely etched. Some parts of the surface of the transparent conductive layer 4 are etched, and other parts of the surface of the transparent conductive layer 4 are not etched, whereby the embossed and depressed patterns 6 are formed at the surface of the transparent conductive layer 4. Moreover, the embossed and depressed patterns 6 are more embossed or depressed due to the difference between the crystallized portions and the amorphous portions.
In FIG. 1C, the transparent conductive layer 4 of FIG. 1B is patterned by irradiating a laser beam to the transparent conductive layer 4 including the embossed and depressed patterns 6 using a laser (not shown), and thus a transparent electrode 8 is formed in each unit cell. The transparent electrode 8 in one unit cell is spaced apart from one in a next unit cell.
In FIG. 1D, an n-type semiconductor layer 10 is formed on a substantially entire surface of the substrate 1 including the transparent electrodes 8 by depositing a semiconductor material with n-type impurities. Subsequently, a p-type semiconductor layer 15 is formed on the n-type semiconductor layer 10 by depositing a semiconductor material with p-type impurities. The n-type semiconductor layer 10 and the p-type semiconductor layer 15 constitute a p-n junction semiconductor layer 20.
In FIG. 1E, the p-n junction semiconductor layer 20 is patterned by irradiating a laser beam to the p-n junction semiconductor layer 20 using a laser (not shown).
In FIG. 1F, a rear electrode 30 is formed on the patterned p-n junction semiconductor layer 20 by depositing a metallic material all over the surface and patterning it. Accordingly, a solar cell 50 is completed.
However, in the solar cell 50, the embossed and depressed patterns 6 are small and irregular.
FIG. 2 is a cross-sectional view of enlarging part of a related art solar cell. In FIG. 2, the embossed and depressed patterns 6 are formed by etching the transparent conductive layer 4 using different etch rates of the crystallized portions and the amorphous portions, which are formed when the transparent conductive material is deposited. Here, the crystallized portions are randomly disposed, and the micro-crystallization is performed. Therefore, the embossed patterns 6 are very small, and angles of sides of the embossed patterns 6 with respect to the substrate 1 are irregular. According to this, incident light through a surface of the substrate 1 is not effectively scattered, and the efficiency of the solar cell 50 is lowered.